The downscaling of integrated circuit devices, and in particular multilevel interconnect structures, has required concerted efforts to reduce electrical resistance while maintaining current densities For filling high aspect conductive patterns such as trenches, vias, contacts and other features, bulk copper has been applied using electrochemical deposition (ECD) over a sputtered copper seed layer to achieve plated copper adhesion, microstructure, and electromigration characteristics. Multiple barrier layers have been utilized to prevent copper diffusion into the substrate. In one approach, tantalum-tantalum nitride barriers have been used for their ability to prevent diffusion into the lower dielectric substrates. Atomic layer deposition of a discrete layer of tantalum nitride as a diffusion barrier overlaid with a discrete layer ruthenium as an adhesion layer has also been proposed as disclosed in U.S. Pat. No. 7,273,814. Both multiple layer barriers and the attendant seed layer are necessarily complex and relatively thick limiting the down scaling of interconnect structures in nanoelectronics. The application of direct plating of copper on a diffusion barrier without the need for discrete copper nucleation and seed layers has been recognized as an approach for reducing interconnect thickness (ref. 1). Unfortunately, none of the materials known to be appropriate for direct copper plating, such as Ru, Pt, or Ir, also serve as robust barrier materials, primarily due to microstructural issues (ref. 2). Likewise, candidate barrier materials such as TaN and TaSiN are not appropriate for direct plating due to their surface chemistry characteristics (3). Each layer must possess a minimal thickness of several nanometers, intrinsically limiting the minimum thickness of the dual layer approach. Accordingly, it would be desirable to provide reduced thickness diffusion barriers that can be directly copper plated.